Binarized Neural Network with Silicon Nanosheet Synaptic Transistors for Supervised Pattern Classification.


Journal

Scientific reports
ISSN: 2045-2322
Titre abrégé: Sci Rep
Pays: England
ID NLM: 101563288

Informations de publication

Date de publication:
12 08 2019
Historique:
received: 22 02 2019
accepted: 29 07 2019
entrez: 14 8 2019
pubmed: 14 8 2019
medline: 14 8 2019
Statut: epublish

Résumé

In the biological neural network, the learning process is achieved through massively parallel synaptic connections between neurons that can be adjusted in an analog manner. Recent developments in emerging synaptic devices and their networks can emulate the functionality of a biological neural network, which will be the fundamental building block for a neuromorphic computing architecture. However, on-chip implementation of a large-scale artificial neural network is still very challenging due to unreliable analog weight modulation in current synaptic device technology. Here, we demonstrate a binarized neural network (BNN) based on a gate-all-around silicon nanosheet synaptic transistor, where reliable digital-type weight modulation can contribute to improve the sustainability of the entire network. BNN is applied to three proof-of-concept examples: (1) handwritten digit classification (MNIST dataset), (2) face image classification (Yale dataset), and (3) experimental 3 × 3 binary pattern classifications using an integrated synaptic transistor network (total 9 × 9 × 2   162 cells) through a supervised online training procedure. The results consolidate the feasibility of binarized neural networks and pave the way toward building a reliable and large-scale artificial neural network by using more advanced conventional digital device technologies.

Identifiants

pubmed: 31406242
doi: 10.1038/s41598-019-48048-w
pii: 10.1038/s41598-019-48048-w
pmc: PMC6690903
doi:

Types de publication

Journal Article Research Support, Non-U.S. Gov't

Langues

eng

Sous-ensembles de citation

IM

Pagination

11705

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Auteurs

Sungho Kim (S)

Department of Electrical Engineering, Sejong University, Seoul, 05006, Korea.

Bongsik Choi (B)

School of Electrical Engineering, Kookmin University, Seoul, 02707, Korea.

Jinsu Yoon (J)

School of Electrical Engineering, Kookmin University, Seoul, 02707, Korea.

Yongwoo Lee (Y)

School of Electrical Engineering, Kookmin University, Seoul, 02707, Korea.

Hee-Dong Kim (HD)

Department of Electrical Engineering, Sejong University, Seoul, 05006, Korea.

Min-Ho Kang (MH)

Department of Nano-process, National Nanofab Center (NNFC), Daejeon, 34141, Korea.

Sung-Jin Choi (SJ)

School of Electrical Engineering, Kookmin University, Seoul, 02707, Korea. sjchoiee@kookmin.ac.kr.

Classifications MeSH