Memristive and CMOS Devices for Neuromorphic Computing.

Flash memories artificial neural network memristive devices neuromorphic computing pattern recognition resistive switching spiking neural network synaptic plasticity

Journal

Materials (Basel, Switzerland)
ISSN: 1996-1944
Titre abrégé: Materials (Basel)
Pays: Switzerland
ID NLM: 101555929

Informations de publication

Date de publication:
01 Jan 2020
Historique:
received: 28 11 2019
revised: 17 12 2019
accepted: 18 12 2019
entrez: 8 1 2020
pubmed: 8 1 2020
medline: 8 1 2020
Statut: epublish

Résumé

Neuromorphic computing has emerged as one of the most promising paradigms to overcome the limitations of von Neumann architecture of conventional digital processors. The aim of neuromorphic computing is to faithfully reproduce the computing processes in the human brain, thus paralleling its outstanding energy efficiency and compactness. Toward this goal, however, some major challenges have to be faced. Since the brain processes information by high-density neural networks with ultra-low power consumption, novel device concepts combining high scalability, low-power operation, and advanced computing functionality must be developed. This work provides an overview of the most promising device concepts in neuromorphic computing including complementary metal-oxide semiconductor (CMOS) and memristive technologies. First, the physics and operation of CMOS-based floating-gate memory devices in artificial neural networks will be addressed. Then, several memristive concepts will be reviewed and discussed for applications in deep neural network and spiking neural network architectures. Finally, the main technology challenges and perspectives of neuromorphic computing will be discussed.

Identifiants

pubmed: 31906325
pii: ma13010166
doi: 10.3390/ma13010166
pmc: PMC6981548
pii:
doi:

Types de publication

Journal Article Review

Langues

eng

Subventions

Organisme : H2020 European Research Council
ID : 648635

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Auteurs

Valerio Milo (V)

Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano and Italian Universities Nanoelectronics Team (IU.NET), Piazza L. da Vinci 32, 20133 Milano, Italy.

Gerardo Malavena (G)

Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano and Italian Universities Nanoelectronics Team (IU.NET), Piazza L. da Vinci 32, 20133 Milano, Italy.

Christian Monzio Compagnoni (C)

Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano and Italian Universities Nanoelectronics Team (IU.NET), Piazza L. da Vinci 32, 20133 Milano, Italy.

Daniele Ielmini (D)

Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano and Italian Universities Nanoelectronics Team (IU.NET), Piazza L. da Vinci 32, 20133 Milano, Italy.

Classifications MeSH