Gate-all-around nanowire vertical tunneling FETs by ferroelectric internal voltage amplification.

Hf0.5Zr0.5O2 Si0.6Ge0.4 gate-all-around internal voltage nanowire optimized metal–ferroelectric–semiconductor vertical tunneling

Journal

Nanotechnology
ISSN: 1361-6528
Titre abrégé: Nanotechnology
Pays: England
ID NLM: 101241272

Informations de publication

Date de publication:
12 Nov 2021
Historique:
received: 05 08 2021
accepted: 08 10 2021
pubmed: 9 10 2021
medline: 9 10 2021
entrez: 8 10 2021
Statut: epublish

Résumé

This work illustrates the most effective way of utilizing the ferroelectricity for tunneling field-effect transistors (TFETs). The ferroelectric (Hf

Identifiants

DOI: 10.1088/1361-6528/ac2e26 PMID: 34624872
pubmed: 34624872
doi: 10.1088/1361-6528/ac2e26
doi:

Types de publication

Journal Article

Langues

eng

Sous-ensembles de citation

IM

Informations de copyright

© 2021 IOP Publishing Ltd.

Auteurs

Narasimhulu Thoti (N)

Parallel and Scientific Computing Laboratory, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan.
EECS International Graduate Program, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan.
Department of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan.
ORCID: 0000-0003-4011-5403

Yiming Li (Y)

Parallel and Scientific Computing Laboratory, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan.
EECS International Graduate Program, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan.
Department of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan.
Institute of Communications Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan.
Institute of Biomedical Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan.
ORCID: 0000-0001-7374-0964

Classifications MeSH