The Schottky barrier transistor in emerging electronic devices.

1D materials 2D materials Josephson junctions Schottky barriers field effect transistors source-gated transistors thin film transistors

Journal

Nanotechnology
ISSN: 1361-6528
Titre abrégé: Nanotechnology
Pays: England
ID NLM: 101241272

Informations de publication

Date de publication:
15 Jun 2023
Historique:
received: 30 09 2022
accepted: 25 04 2023
medline: 27 4 2023
pubmed: 27 4 2023
entrez: 26 4 2023
Statut: epublish

Résumé

This paper explores how the Schottky barrier (SB) transistor is used in a variety of applications and material systems. A discussion of SB formation, current transport processes, and an overview of modeling are first considered. Three discussions follow, which detail the role of SB transistors in high performance, ubiquitous and cryogenic electronics. For high performance computing, the SB typically needs to be minimized to achieve optimal performance and we explore the methods adopted in carbon nanotube technology and two-dimensional electronics. On the contrary for ubiquitous electronics, the SB can be used advantageously in source-gated transistors and reconfigurable field-effect transistors (FETs) for sensors, neuromorphic hardware and security applications. Similarly, judicious use of an SB can be an asset for applications involving Josephson junction FETs.

Identifiants

pubmed: 37100049
doi: 10.1088/1361-6528/acd05f
doi:

Types de publication

Journal Article Review

Langues

eng

Sous-ensembles de citation

IM

Informations de copyright

Creative Commons Attribution license.

Auteurs

Mike Schwarz (M)

THM University of Applied Sciences, Germany.

Tom D Vethaak (TD)

Department of Microtechnology and Nanoscience, Chalmers University of Technology, SE-412 96 Gothenburg, Sweden.

Vincent Derycke (V)

Université Paris-Saclay, CEA, CNRS, NIMBE, LICSEN, Gif-sur-Yvette, F-91191, France.

Anaïs Francheteau (A)

University Grenoble Alps, GINP, CEA-IRIG-PHELIQS, Grenoble, France.

Benjamin Iniguez (B)

Universitaet Rovira i Virgili (URV), Spain.

Satender Kataria (S)

RWTH Aachen, Germany.

Alexander Kloes (A)

THM University of Applied Sciences, Germany.

Francois Lefloch (F)

University Grenoble Alps, GINP, CEA-IRIG-PHELIQS, Grenoble, France.

John P Snyder (JP)

JCap, LLC, United States of America.

Walter M Weber (WM)

Technische Universität Wien, Institute of Solid State Electronics, Vienna, Austria.

Laurie E Calvet (LE)

LPICM, CNRS-Ecole Polytechnique, Palaiseau, France.

Classifications MeSH