Multi-Level Resistive Al/Ga

RRAM bilayer structure gallium oxide graphene oxide multi-level storage

Journal

Nanomaterials (Basel, Switzerland)
ISSN: 2079-4991
Titre abrégé: Nanomaterials (Basel)
Pays: Switzerland
ID NLM: 101610216

Informations de publication

Date de publication:
13 Jun 2023
Historique:
received: 05 05 2023
revised: 07 06 2023
accepted: 12 06 2023
medline: 27 6 2023
pubmed: 27 6 2023
entrez: 27 6 2023
Statut: epublish

Résumé

Recently, resistive random access memory (RRAM) has been an outstanding candidate among various emerging nonvolatile memories for high-density storage and in-memory computing applications. However, traditional RRAM, which accommodates two states depending on applied voltage, cannot meet the high density requirement in the era of big data. Many research groups have demonstrated that RRAM possesses the potential for multi-level cells, which would overcome demands related to mass storage. Among numerous semiconductor materials, gallium oxide (a fourth-generation semiconductor material) is applied in the fields of optoelectronics, high-power resistive switching devices, and so on, due to its excellent transparent material properties and wide bandgap. In this study, we successfully demonstrate that Al/graphene oxide (GO)/Ga

Identifiants

pubmed: 37368281
pii: nano13121851
doi: 10.3390/nano13121851
pmc: PMC10302128
pii:
doi:

Types de publication

Journal Article

Langues

eng

Subventions

Organisme : Ministry of Science and Technology
ID : 108-2221-E-006-040-MY3
Organisme : Ministry of Science and Technology
ID : 111-2221-E-006-206

Références

Nanoscale Res Lett. 2013 Nov 16;8(1):483
pubmed: 24237683
Gels. 2021 Dec 27;8(1):
pubmed: 35049555
Materials (Basel). 2020 Jan 12;13(2):
pubmed: 31940894
Nanoscale Res Lett. 2020 Apr 22;15(1):90
pubmed: 32323059
Nanoscale Res Lett. 2014 Sep 25;9(1):526
pubmed: 25278820
Nanomaterials (Basel). 2022 Sep 19;12(18):
pubmed: 36145040
Small. 2018 Jun 21;:e1801325
pubmed: 29931801

Auteurs

Li-Wen Wang (LW)

Department of Electrical Engineering, National Cheng-Kung University, Tainan 701, Taiwan.

Chih-Wei Huang (CW)

Institute of Microelectronics, Department of Electrical Engineering, National Cheng-Kung University, Tainan 701, Taiwan.

Ke-Jing Lee (KJ)

Institute of Microelectronics, Department of Electrical Engineering, National Cheng-Kung University, Tainan 701, Taiwan.
Program on Semiconductor Process Technology, Academy of Innovative Semiconductor and Sustainable Manufacturing, National Cheng-Kung University, Tainan 701, Taiwan.

Sheng-Yuan Chu (SY)

Department of Electrical Engineering, National Cheng-Kung University, Tainan 701, Taiwan.

Yeong-Her Wang (YH)

Institute of Microelectronics, Department of Electrical Engineering, National Cheng-Kung University, Tainan 701, Taiwan.
Program on Semiconductor Process Technology, Academy of Innovative Semiconductor and Sustainable Manufacturing, National Cheng-Kung University, Tainan 701, Taiwan.

Classifications MeSH