Digital Hardware Implementation of ReSuMe Learning Algorithm for Spiking Neural Networks.
Journal
Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference
ISSN: 2694-0604
Titre abrégé: Annu Int Conf IEEE Eng Med Biol Soc
Pays: United States
ID NLM: 101763872
Informations de publication
Date de publication:
Jul 2023
Jul 2023
Historique:
medline:
12
12
2023
pubmed:
12
12
2023
entrez:
12
12
2023
Statut:
ppublish
Résumé
Within this paper, we demonstrate the feasibility of the FPGA implementation as well as the 180nm CMOS circuit design of a particular biologically plausible supervised learning algorithm (ReSuMe). Based on the Spike-Timing-Dependent Plasticity (STDP) learning phenomenon, this design proposes a fully configurable implementation of STDP learning window function to adjust the learning process for different applications, optimizing results for each use case. The CMOS implementation in 180nm technology node supplied with 1.8V shows a core area of 0.78mm
Identifiants
pubmed: 38083592
doi: 10.1109/EMBC40787.2023.10340282
doi:
Types de publication
Journal Article
Langues
eng
Sous-ensembles de citation
IM