A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications.

Journal

Scientific reports

ISSN: 2045-2322

Titre abrégé: Sci Rep

Pays: England

ID NLM: 101563288

Informations de publication

Date de publication:
16 Dec 2023

Historique:

received: 25 08 2023

accepted: 13 12 2023

medline: 17 12 2023

pubmed: 17 12 2023

entrez: 16 12 2023

Statut: epublish

Résumé

A technique for efficiently multiplying two signed numbers using limited area and high speed is presented in this paper. This work uses both the Booth and Vedic multiplication sutra methodologies to enhance the speed and reduction in the area by using two VLSI architectures of radix encoding techniques-Radix-4 and Radix-8-with the Vedic multiplier. The functionality of the proposed methods is tested using an Artix-7 Field Programmable Gate Array (FPGA-XC7A100T-CSG324) in Xilinx Vivado 2019.1 and ASIC 45 nm technology. Two methods of Booth encoding using Vedic multiplier (Urdhva-Tiryakbhyam sutra) were used to develop, and examine the benefits of rapid computational multiplier. The results of the proposed multiplier for Booth-Vedic-Radix-4 encoding (BVR-4) decrease area by 89% and improve Area-Delay Product (ADP) by 72% for a 16-bit multiplier when subjected to other existing multipliers. The Booth-Vedic-Radix-8 (BVR-8) method shows that there will be an 89% reduction in area and an improvement in ADP by 72% for the 16-bit multiplier. The performance is evaluated regarding area occupancy (i.e., LUTs number) and propagation delay (output time). In terms of resource utilization, the proposed BVR-4 and BVR-8 multipliers outperform all the current designs with a marginal effect on speed and area for narrower bit-width ranges.

Identifiants

DOI: 10.1038/s41598-023-49913-5 PMID: 38104192

pubmed: 38104192

doi: 10.1038/s41598-023-49913-5

pii: 10.1038/s41598-023-49913-5

doi:

Types de publication

Journal Article

Langues

eng

Sous-ensembles de citation

Pagination

22379

Informations de copyright

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