Analog reservoir computing via ferroelectric mixed phase boundary transistors.


Journal

Nature communications
ISSN: 2041-1723
Titre abrégé: Nat Commun
Pays: England
ID NLM: 101528555

Informations de publication

Date de publication:
23 Oct 2024
Historique:
received: 30 04 2024
accepted: 08 10 2024
medline: 24 10 2024
pubmed: 24 10 2024
entrez: 23 10 2024
Statut: epublish

Résumé

Analog reservoir computing (ARC) systems have attracted attention owing to their efficiency in processing temporal information. However, the distinct functionalities of the system components pose challenges for hardware implementation. Herein, we report a fully integrated ARC system that leverages material versatility of the ferroelectric-to-mixed phase boundary (MPB) hafnium zirconium oxides integrated onto indium-gallium-zinc oxide thin-film transistors (TFTs). MPB-based TFTs (MPBTFTs) with nonlinear short-term memory characteristics are utilized for physical reservoirs and artificial neuron, while nonvolatile ferroelectric TFTs mimic synaptic behavior for readout networks. Furthermore, double-gate configuration of MPBTFTs enhances reservoir state differentiation and state expansion for physical reservoir and processes both excitatory and inhibitory pulses for neuronal functionality with minimal hardware burden. The seamless integration of ARC components on a single wafer executes complex real-world time-series predictions with a low normalized root mean squared error of 0.28. The material-device co-optimization proposed in this study paves the way for the development of area- and energy-efficient ARC systems.

Identifiants

pubmed: 39443502
doi: 10.1038/s41467-024-53321-2
pii: 10.1038/s41467-024-53321-2
doi:

Types de publication

Journal Article

Langues

eng

Sous-ensembles de citation

IM

Pagination

9147

Subventions

Organisme : National Research Foundation of Korea (NRF)
ID : RS-2023-00260527

Informations de copyright

© 2024. The Author(s).

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Auteurs

Jangsaeng Kim (J)

Department of Electronic Engineering, Hanyang University, Seoul, 04763, Republic of Korea.
Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA, 02139, USA.
Department of Electrical and Computer Engineering and Inter-university Semiconductor Research Center, Seoul National University, Seoul, 08826, Republic of Korea.

Eun Chan Park (EC)

Department of Electronic Engineering, Hanyang University, Seoul, 04763, Republic of Korea.

Wonjun Shin (W)

Department of Electrical and Computer Engineering and Inter-university Semiconductor Research Center, Seoul National University, Seoul, 08826, Republic of Korea.
Department of Semiconductor Convergence Engineering, Sungkyunkwan University, Suwon, 16419, Republic of Korea.

Ryun-Han Koo (RH)

Department of Electrical and Computer Engineering and Inter-university Semiconductor Research Center, Seoul National University, Seoul, 08826, Republic of Korea.

Chang-Hyeon Han (CH)

Department of Electronic Engineering, Hanyang University, Seoul, 04763, Republic of Korea.

He Young Kang (HY)

Department of Electronic Engineering, Hanyang University, Seoul, 04763, Republic of Korea.

Tae Gyu Yang (TG)

Department of Electronic Engineering, Hanyang University, Seoul, 04763, Republic of Korea.

Youngin Goh (Y)

Semiconductor Research and Development Center, Samsung Electronics, Hwaseong, Republic of Korea.

Kilho Lee (K)

Semiconductor Research and Development Center, Samsung Electronics, Hwaseong, Republic of Korea.

Daewon Ha (D)

Semiconductor Research and Development Center, Samsung Electronics, Hwaseong, Republic of Korea.

Suraj S Cheema (SS)

Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA, 02139, USA. sscheema@mit.edu.

Jae Kyeong Jeong (JK)

Department of Electronic Engineering, Hanyang University, Seoul, 04763, Republic of Korea. jkjeong1@hanyang.ac.kr.

Daewoong Kwon (D)

Department of Electronic Engineering, Hanyang University, Seoul, 04763, Republic of Korea. dw79kwon@hanyang.ac.kr.

Classifications MeSH